Why is serial faster than parallel

Serial transmission is slower than parallel transmission given the same signal frequency. With a parallel transmission you can transfer one word per cycle e. You cannot increase the signal frequency for a parallel transmission without limit, because, by design, all signals from the transmitter need to arrive at the receiver at the same time.

This cannot be guaranteed for high frequencies, as you cannot guarantee that the signal transit time is equal for all signal lines think of different paths on the mainboard. The higher the frequency, the more tiny differences matter. Between chips on a circuit board, a serial protocol like I2C that needs only two wires is much easier to deal with than routing numerous parallel traces. But there are plenty of examples inside your computer where parallelism is used to massively increase the bandwidth.

For instance, words are not read one bit at a time from memory. And in fact, caches are refilled in large blocks. Raster displays are another example: parallel access to multiple memory banks to get the pixels faster, in parallel. Memory bandwith depends critically on parallelism. If the world's fastest 10 bit DAC could be made using a single serial input line, then it probably would. If you're already toggling the wire as fast as your transistor allows, so the only way to scale is using more wires.

With time, Moore's law outpaced the electromagnetic constrains so transmissions over cables, or even on-board buses, became a bottleneck compared to on-chip speeds. OTOH, the speed disparity allows sophisticated processing at the ends to use the channel more effectively. Induced noise, aka crosstalk, goes up with frequency. I think this is what caused the "serial is faster that parallel" impression — the jump was so large that you could go down to 1 or 2 differential pairs and still be faster than LPT or IDE cables.

There was also a crosstalk win from having only one signal pair in the cable, but that's minor. Encoding the data to avoid streaks of 0s or 1s incurs a small overhead but has electric benefits avoids DC drift, controls spectrum and most importantly allows dropping the clock wire s altogether which isn't a big deal on top of 40 signals but is a huge deal for a serial cable to have 1 or 2 pairs instead of 2 or 3.

Note that we are throwing parallelism at the bottleneck — today's BGA chips have hundreds or thousands of pins, PCBs have more and more layers. Compare this to old pin microcontrollers and 2 layer PCBs Most of the above techniques became indispensable for both parallel and serial transmission. It's just that the longer the wires, the more attractive it becomes to push higher rates through fewer wires. Sign up to join this community.

The best answers are voted up and rise to the top. Stack Overflow for Teams — Collaborate and share knowledge with a private group. Create a free Team What is Teams? Learn more. Why is serial data transmission faster than parallel? Ask Question. Asked 8 years, 5 months ago. Active 6 years, 5 months ago. Viewed 66k times.

Improve this question. Hennes Maybe it is, but if so, howcome I see all these intel. It all boils down to clock rate. The existing three answers fail to mention economics, i. It is simply cheaper to make a very-fast serial interface than a very-fast parallel interface. For transmission lines, a serial cable that uses just a few wires is cheaper than a parallel cable that will be difficult and expensive to shield.

Add a comment. Active Oldest Votes. You cannot formulate it this way. But in optical fiber we can use different wavelength signals through the same fiber. You could call that parallel. With serial "all you have to do", is be able to is extract the clock and as a result the data. Yes, absolutely that one serial interface has to run N times faster than an N wide parallel bus in order to be "faster" but a long time ago now we reached that point.

Each of these lanes is an independent serial interface taking advantage of the "serial speed", but the overall transmission of data is split up load balanced down the separate serial interfaces, then combined as needed on the other side. Obviously one serial interface can go no faster than one bit lane of a parallel bus all other things held constant. The key is with speed, routing, cables, connectors, etc keeping the bits parallel and meeting setup and hold times at the far end is the problem.

You can easily run N times faster using one serial interface. Then there is the real estate from pins to pcboard to connectors. Costing half-ish the copper or fiber in the cables and elsewhere. That marginal cost in server farms was enough to abandon the traditional path for industry standards and go off and whip one up on the side and roll it out in a hurry. Pcie likewise, started with one or more serial interfaces with the data load balanced.

Still uses serial lanes with the data load balanced an rejoined, the speeds increase each generation per serial interface rather than adding more and more serial pairs. SATA is the serial version of PATA which is a direct decendent to IDE, not that serial was faster just that it is far easier to sync up with and extract a serial stream than it is to keep N parallel bits in sync from one end to the next.

And remains easier to transmit and extract even if the serial stream is per bit lane 16, 32, 64, or more times faster than the parallel. The shift is from "parallel on a single clock" to "multiple serial links". Such as PCIe, where a card may have 1x to 16x "lanes". Adding more connectors makes both the cable, its connectors and the receptacles on each device larger and more expensive.

You're not going to see a phone with a Centronics connector on. So as the devices get smaller there's pressure for smaller interfaces with fewer cables. The devices have also got faster with better signal processing. So it's now possible to have much higher bitrates.

However, this has a disadvantage for traditional parallel links: skew. Skew is the difference in arrival times between signals in a group. The traditional parallel link has a single clock for all signals. It assumes that the clock and signals all arrive at roughly the same time. As the signals get faster, the tiny differences in arrival times become more important.

This means that a wide parallel connection is limited in speed: you have to go slowly enough that all bits arrive within the same time window and are not overwritten by the next bit coming along. Wikipedia has an article with a list of x86 CPU sockets by year.